Description
Insufficient DRAM address validation in System Management Unit (SMU) may result in a DMA read from invalid DRAM address to SRAM resulting in SMU not servicing further requests.
Affected products
| Vendor | Product | Affected | Fixed |
|---|---|---|---|
| AMD | Ryzen™ Series | various | — |
| AMD | Athlon™ Series | various | — |
Advisories 1
- WID-SEC-2022-0073 AMD Prozessoren: Mehrere Schwachstellen BSI CERT-Bund (WID) · Feb 16, 2025