Description
Improper re-initialization of IOMMU during the DRTM event
may permit an untrusted platform configuration to persist, allowing an attacker
to read or modify hypervisor memory, potentially resulting in loss of
confidentiality, integrity, and availability.
Affected products
| Vendor | Product | Affected | Fixed |
|---|---|---|---|
| AMD | AMD EPYC™ 7003 Series Processors | — | MilanPI 1.0.0.B |
| AMD | AMD EPYC™ 9004 Series Processors | — | Genoa 1.0.0.8 |
| AMD | AMD EPYC™ Embedded 7003 Series Processors | — | EmbMilanPI-SP3 1.0.0.7 |
| AMD | AMD EPYC™ Embedded 9003 Series Processors | — | EmbGenoaPI-SP5 1.0.0.3 |
Advisories 1
- WID-SEC-2024-1837 AMD Prozessoren: Mehrere Schwachstellen BSI CERT-Bund (WID) · May 12, 2026