Critical · 9.1 CVE-2025-45006 EUVD-2025-19672GHSA-9mrj-rvvj-725q

Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling…

Published Jul 1, 2025 · Updated Jul 2, 2025 · Assigned by mitre

Description

Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.

References

https://github.com/chipsalliance/rocket-chip.git
https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications
https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-45006/details.md