Summary
It was discovered that some Intel® Core™ Ultra Processors did not properly
isolate the stream cache. A local authenticated user could potentially use
this to escalate their privileges. (CVE-2023-42667)
It was discovered that some Intel® Processors did not properly isolate the
stream cache. A local authenticated user could potentially use this to
escalate their privileges. (CVE-2023-49141)
It was discovered that some Intel® Processors did not correctly transition
between the executive monitor and SMI transfer monitor (STM). A privileged
local attacker could use this to escalate their privileges.
(CVE-2024-24853)
It was discovered that some 3rd, 4th, and 5th Generation Intel® Xeon®
Processors failed to properly implement a protection mechanism. A local
attacker could use this to potentially escalate their privileges.
(CVE-2024-24980)
It was discovered that some 3rd Generation Intel Xeon Scalable Processors
did not properly handle mirrored regions with different values. A
privileged local user could use this to cause a denial of service (system
crash). (CVE-2024-25939)
Fixed packages 5
| Release | Package | Fixed in |
|---|---|---|
| Ubuntu · 20.04 LTS 20.04:LTS | intel-microcode | 3.20240813.0ubuntu0.20.04.2 |
| Ubuntu · 22.04 LTS 22.04:LTS | intel-microcode | 3.20240813.0ubuntu0.22.04.2 |
| Ubuntu · 24.04 LTS 24.04:LTS | intel-microcode | 3.20240813.0ubuntu0.24.04.2 |
| Ubuntu · Pro 16.04 LTS Pro:16.04:LTS | intel-microcode | 3.20240813.0ubuntu0.16.04.1+esm2 |
| Ubuntu · Pro 18.04 LTS Pro:18.04:LTS | intel-microcode | 3.20240813.0ubuntu0.18.04.1+esm2 |
Vulnerabilities 5
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High 7.8
Improper isolation in the Intel(R) Core(TM) Ultra Processor stream cache mechanism may allow an authenticated user to p…
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High 7.8
Improper isolation in some Intel(R) Processors stream cache mechanism may allow an authenticated user to potentially en…
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High 7.2
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Proces…
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Medium 6.1
Protection mechanism failure in some 3rd, 4th, and 5th Generation Intel(R) Xeon(R) Processors may allow a privileged us…
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Medium 6.0
Mirrored regions with different values in 3rd Generation Intel(R) Xeon(R) Scalable Processors may allow a privileged us…