67 results · Feed
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Medium 4.0
Exposure of sensitive information caused by incorrect data forwarding during transient execution for some Intel(R) Proc…
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Medium 4.5
Improper handling of values for some Intel(R) Processors within Ring 0: Kernel, Hypervisor and Bare Metal OS may allow …
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Medium 6.8
Improper handling of overlap between protected memory ranges in some microcode for some Intel(R) Processors within Ring…
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High 7.2
Improper access control for some Intel(R) Processors within Ring 3: User Applications may allow an escalation of privil…
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Medium 4.5
Always-incorrect control flow implementation in some firmware for some Intel(R) Xeon(R) processors may allow an escalat…
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Medium 6.8
Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient executi…
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Low 3.9
Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privile…
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High 7.2
Improperly implemented security check for standard in the DDRIO configuration for some Intel(R) Xeon(R) 6 Processors wh…
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High 7.2
Out-of-bounds write in the memory subsystem for some Intel(R) Xeon(R) 6 processors when using Intel(R) SGX or Intel(R) …
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High 7.2
Insufficient control flow management in the Alias Checking Trusted Module (ACTM) firmware for some Intel(R) Xeon(R) pro…
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High 7.9
Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processor with Intel(R) TDX ma…
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High 7.4
Sequence of processor instructions leads to unexpected behavior for some Intel(R) Xeon(R) 6 Scalable processors may all…
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High 7.5
Insufficient granularity of access control in the OOB-MSM for some Intel(R) Xeon(R) 6 Scalable processors may allow a p…
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Medium 6.5
Missing reference to active allocated resource for some Intel(R) Xeon(R) processors may allow an authenticated user to …
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High 7.8
Improper Isolation or Compartmentalization in the stream cache mechanism for some Intel(R) Processors may allow an auth…
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High 7.2
Improper buffer restrictions for some Intel(R) Xeon(R) Processor firmware with SGX enabled may allow a privileged user …
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Medium 5.6
Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient executi…
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Medium 5.6
Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient executi…
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Medium 5.6
Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel(R) …
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Medium 5.6
Incorrect initialization of resource in the branch prediction unit for some Intel(R) Core™ Ultra Processors may allow a…
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Medium 5.6
Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient executi…
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Medium 6.5
Insufficient resource pool in the core management mechanism for some Intel(R) Processors may allow an authenticated use…
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Medium 6.5
Uncaught exception in the core management mechanism for some Intel(R) Processors may allow an authenticated user to pot…
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Medium 4.9
Incorrect behavior order for some Intel(R) Core™ Ultra Processors may allow an unauthenticated user to potentially enab…
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Medium 5.3
Improper Finite State Machines (FSMs) in Hardware Logic for some Intel(R) Processors may allow privileged user to poten…
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Medium 6.5
Improper access control in the EDECCSSA user leaf function for some Intel(R) Processors with Intel(R) SGX may allow an …
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Low 3.8
Sequence of processor instructions leads to unexpected behavior in the Intel(R) DSA V1.0 for some Intel(R) Xeon(R) Proc…
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Medium 6.5
Improper handling of physical or environmental conditions in some Intel(R) Processors may allow an authenticated user t…
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High 8.2
Improper input validation in UEFI firmware for some Intel(R) processors may allow a privileged user to potentially enab…
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Medium 4.7
Improper finite state machines (FSMs) in the hardware logic in some 4th and 5th Generation Intel(R) Xeon(R) Processors …
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High 8.8
Improper conditions check in some Intel(R) Xeon(R) processor memory controller configurations when using Intel(R) SGX m…
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Medium 5.3
Observable discrepancy in RAPL interface for some Intel(R) Processors may allow a privileged user to potentially enable…
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Medium 5.3
Improper finite state machines (FSMs) in hardware logic in some Intel(R) Processors may allow an privileged user to pot…
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High 7.8
Improper isolation in the Intel(R) Core(TM) Ultra Processor stream cache mechanism may allow an authenticated user to p…
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High 7.8
Improper isolation in some Intel(R) Processors stream cache mechanism may allow an authenticated user to potentially en…
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High 7.2
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Proces…
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Medium 6.1
Protection mechanism failure in some 3rd, 4th, and 5th Generation Intel(R) Xeon(R) Processors may allow a privileged us…
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Medium 6.0
Mirrored regions with different values in 3rd Generation Intel(R) Xeon(R) Scalable Processors may allow a privileged us…
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High 7.9
Improper input validation in some Intel(R) TDX module software before version 1.5.05.46.698 may allow a privileged user…
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Low 2.8
Hardware logic contains race conditions in some Intel(R) Processors may allow an authenticated user to potentially enab…