Weakness (CWE)
CWE-1332: Improper Handling of Faults that Lead to Instruction Skips
The device is missing or incorrectly implements circuitry or sensors that detect and mitigate the skipping of security-critical CPU instructions when they occur.
How to prevent it (6 mitigations)
-
Architecture and Design
Design strategies for ensuring safe failure if
inputs, such as Vcc, are modified out of acceptable
ranges. -
Architecture and Design
Design strategies for ensuring safe behavior if
instructions attempt to be skipped. -
Architecture and Design
Identify mission critical secrets that should
be wiped if faulting is detected, and design a
mechanism to do the deletion. -
Implementation
Add redundancy by performing an operation
multiple times, either in space or time, and perform
majority voting. Additionally, make conditional
instruction timing unpredictable. -
Implementation
Use redundant operations or canaries to
detect and respond to faults. -
Implementation
Ensure that fault mitigations are strong enough
in practice. For example, a low power detection
mechanism that takes 50 clock cycles to trigger at lower
voltages may be an insufficient security mechanism if
the instruction counter has already progressed with no
other CPU activity occurring.
Source: MITRE CWE-1332
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