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Weakness (CWE)

CWE-1342: Information Exposure through Microarchitectural State after Transient Execution

Base Incomplete

The processor does not properly clear microarchitectural state after incorrect microcode assists or speculative execution, resulting in transient execution.

More detail

In many processor architectures an exception, mis-speculation, or microcode assist results in a flush operation to clear results that are no longer required. This action prevents these results from influencing architectural state that is intended to be visible from software. However, traces of this transient execution may remain in microarchitectural buffers, resulting in a change in microarchitectural state that can expose sensitive information to an attacker using side-channel analysis. For example, Load Value Injection (LVI) [REF-1202] can exploit direct injection of erroneous values into intermediate load and store buffers.

Several conditions may need to be fulfilled for a successful attack:

- incorrect transient execution that results in remanence of sensitive information;

- attacker has the ability to provoke microarchitectural exceptions;

- operations and structures in victim code that can be exploited must be identified.

How to prevent it (2 mitigations)

  1. Architecture and Design, Requirements

    Hardware ensures that no illegal data flows from faulting micro-ops exists at the microarchitectural level.

  2. Build and Compilation

    Include instructions that explicitly remove traces of unneeded computations from software interactions with microarchitectural elements e.g. lfence, sfence, mfence, clflush.

Source: MITRE CWE-1342

All Critical High Medium Low Exploited only Public exploit

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