100 results · Feed
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Medium 4.7
Improper finite state machines (FSMs) in the hardware logic in some 4th and 5th Generation Intel(R) Xeon(R) Processors …
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High 7.2
Incorrect default permissions in some Intel(R) Xeon(R) processor memory controller configurations when using Intel(R) S…
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High 8.8
Improper conditions check in some Intel(R) Xeon(R) processor memory controller configurations when using Intel(R) SGX m…
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Medium 5.3
Observable discrepancy in RAPL interface for some Intel(R) Processors may allow a privileged user to potentially enable…
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Medium 5.3
Improper finite state machines (FSMs) in hardware logic in some Intel(R) Processors may allow an privileged user to pot…
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High 7.8
Improper isolation in the Intel(R) Core(TM) Ultra Processor stream cache mechanism may allow an authenticated user to p…
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High 7.8
Improper isolation in some Intel(R) Processors stream cache mechanism may allow an authenticated user to potentially en…
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High 7.2
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Proces…
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Medium 6.1
Protection mechanism failure in some 3rd, 4th, and 5th Generation Intel(R) Xeon(R) Processors may allow a privileged us…
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Medium 6.0
Mirrored regions with different values in 3rd Generation Intel(R) Xeon(R) Scalable Processors may allow a privileged us…
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Medium 6.0
Improper input validation in some Intel(R) TDX module software before version 1.5.05.46.698 may allow a privileged user…
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High 7.9
Improper input validation in some Intel(R) TDX module software before version 1.5.05.46.698 may allow a privileged user…
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Low 2.8
Hardware logic contains race conditions in some Intel(R) Processors may allow an authenticated user to potentially enab…
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Medium 4.7
Sequence of processor instructions leads to unexpected behavior in Intel(R) Core(TM) Ultra Processors may allow an auth…
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Medium 6.5
Information exposure through microarchitectural state after transient execution from some register files for some Intel…
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Medium 6.5
Protection mechanism failure of bus lock regulator for some Intel(R) Processors may allow an unauthenticated user to po…
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Medium 6.1
Protection mechanism failure in some 3rd and 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Inte…
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Medium 5.5
Non-transparent sharing of return predictor targets between contexts in some Intel(R) Processors may allow an authorize…
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Medium 5.3
Incorrect calculation in microcode keying mechanism for some Intel(R) Xeon(R) D Processors with Intel(R) SGX may allow …
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High 8.8CVE-2023-23583 Public exploit
Sequence of processor instructions leads to unexpected behavior for some Intel(R) Processors may allow an authenticated…
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High 7.2
Unauthorized error injection in Intel(R) SGX or Intel(R) TDX for some Intel(R) Xeon(R) Processors may allow a privilege…
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Medium 6.0
Improper access control in some 3rd Generation Intel(R) Xeon(R) Scalable processors may allow a privileged user to pote…
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Medium 6.5
Information exposure through microarchitectural state after transient execution in certain vector execution units for s…
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Medium 6.0
Improper isolation of shared resources in some Intel(R) Processors when using Intel(R) Software Guard Extensions may al…
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High 7.2
Incorrect default permissions in some memory controller configurations for some Intel(R) Xeon(R) Processors when using …
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Medium 6.1
Incorrect calculation in microcode keying mechanism for some 3rd Generation Intel(R) Xeon(R) Scalable Processors may al…
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High 7.5
Insufficient granularity of access control in out-of-band management in some Intel(R) Atom and Intel Xeon Scalable Proc…
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Medium 5.5
Improper isolation of shared resources in some Intel(R) Processors may allow a privileged user to potentially enable in…
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Medium 5.5
Incomplete cleanup in specific special register write operations for some Intel(R) Processors may allow an authenticate…
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Medium 5.5
Incomplete cleanup in specific special register read operations for some Intel(R) Processors may allow an authenticated…
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Medium 5.5
Incomplete cleanup of microarchitectural fill buffers on some Intel(R) Processors may allow an authenticated user to po…
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Medium 5.5
Incomplete cleanup of multi-core shared buffers for some Intel(R) Processors may allow an authenticated user to potenti…
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Medium 5.5
Processor optimization removal or modification of security-critical code for some Intel(R) Processors may allow an auth…
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Medium 5.5
Improper access control for some 3rd Generation Intel(R) Xeon(R) Scalable Processors before BIOS version MR7, may allow…
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Medium 5.4
Out of bounds read under complex microarchitectural condition in memory subsystem for some Intel Atom(R) Processors may…
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Medium 5.5
Insufficient control flow management in some Intel(R) Processors may allow an authenticated user to potentially enable …
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Medium 5.5
Improper initialization of shared resources in some Intel(R) Processors may allow an authenticated user to potentially …
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Unscored —
Incomplete cleanup in some Intel(R) VT-d products may allow an authenticated user to potentially enable escalation of p…
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Unscored —
Domain-bypass transient execution vulnerability in some Intel Atom(R) Processors may allow an authenticated user to pot…
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Unscored —
Observable timing discrepancy in some Intel(R) Processors may allow an authenticated user to potentially enable informa…