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Medium 4.0
Exposure of sensitive information caused by incorrect data forwarding during transient execution for some Intel(R) Proc…
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Medium 4.0
Improper input validation for some Intel(R) Xeon(R) processors within firmware may allow an escalation of privilege. St…
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Medium 4.5
Improper handling of values for some Intel(R) Processors within Ring 0: Kernel, Hypervisor and Bare Metal OS may allow …
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Medium 4.3
Insufficient granularity of access control in some subsystem for some Intel(R) Xeon(R) 6 Scalable processors with Intel…
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Medium 6.8
Improper handling of overlap between protected memory ranges in some microcode for some Intel(R) Processors within Ring…
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Medium 4.5
Always-incorrect control flow implementation in some firmware for some Intel(R) Xeon(R) processors may allow an escalat…
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Medium 6.8
Hardware logic contains race conditions for some 3rd Gen Intel(R) Xeon(R) Scalable Processors within Ring 3: unprivileg…
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Medium 6.8
Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient executi…
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Medium 6.5
Missing reference to active allocated resource for some Intel(R) Xeon(R) processors may allow an authenticated user to …
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Medium 5.6
Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient executi…
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Medium 5.6
Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient executi…
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Medium 5.6
Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel(R) …
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Medium 5.6
Incorrect initialization of resource in the branch prediction unit for some Intel(R) Core™ Ultra Processors may allow a…
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Medium 5.6
Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient executi…
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Medium 6.5
Insufficient resource pool in the core management mechanism for some Intel(R) Processors may allow an authenticated use…
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Medium 6.5
Uncaught exception in the core management mechanism for some Intel(R) Processors may allow an authenticated user to pot…
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Medium 4.9
Incorrect behavior order for some Intel(R) Core™ Ultra Processors may allow an unauthenticated user to potentially enab…
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Medium 5.3
Improper Finite State Machines (FSMs) in Hardware Logic for some Intel(R) Processors may allow privileged user to poten…
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Medium 6.5
Improper access control in the EDECCSSA user leaf function for some Intel(R) Processors with Intel(R) SGX may allow an …
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Medium 6.5
Insufficient granularity of access control in UEFI firmware in some Intel(R) processors may allow a authenticated user …
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Medium 4.7
Improper finite state machines (FSMs) in the hardware logic in some 4th and 5th Generation Intel(R) Xeon(R) Processors …
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Medium 5.3
Observable discrepancy in RAPL interface for some Intel(R) Processors may allow a privileged user to potentially enable…
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Medium 5.3
Improper finite state machines (FSMs) in hardware logic in some Intel(R) Processors may allow an privileged user to pot…
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Medium 6.1
Protection mechanism failure in some 3rd, 4th, and 5th Generation Intel(R) Xeon(R) Processors may allow a privileged us…
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Medium 6.0
Mirrored regions with different values in 3rd Generation Intel(R) Xeon(R) Scalable Processors may allow a privileged us…
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Medium 6.0
Improper input validation in some Intel(R) TDX module software before version 1.5.05.46.698 may allow a privileged user…
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Medium 4.7
Sequence of processor instructions leads to unexpected behavior in Intel(R) Core(TM) Ultra Processors may allow an auth…
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Medium 6.5
Information exposure through microarchitectural state after transient execution from some register files for some Intel…
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Medium 6.5
Protection mechanism failure of bus lock regulator for some Intel(R) Processors may allow an unauthenticated user to po…
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Medium 6.1
Protection mechanism failure in some 3rd and 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Inte…
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Medium 5.5
Non-transparent sharing of return predictor targets between contexts in some Intel(R) Processors may allow an authorize…
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Medium 5.3
Incorrect calculation in microcode keying mechanism for some Intel(R) Xeon(R) D Processors with Intel(R) SGX may allow …
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Medium 6.0
Improper access control in some 3rd Generation Intel(R) Xeon(R) Scalable processors may allow a privileged user to pote…
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Medium 6.5
Information exposure through microarchitectural state after transient execution in certain vector execution units for s…
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Medium 6.0
Improper isolation of shared resources in some Intel(R) Processors when using Intel(R) Software Guard Extensions may al…
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Medium 6.1
Incorrect calculation in microcode keying mechanism for some 3rd Generation Intel(R) Xeon(R) Scalable Processors may al…
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Medium 5.5
Improper isolation of shared resources in some Intel(R) Processors may allow a privileged user to potentially enable in…
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Medium 5.5
Incomplete cleanup in specific special register write operations for some Intel(R) Processors may allow an authenticate…
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Medium 5.5
Incomplete cleanup in specific special register read operations for some Intel(R) Processors may allow an authenticated…
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Medium 5.5
Incomplete cleanup of microarchitectural fill buffers on some Intel(R) Processors may allow an authenticated user to po…