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Low 3.2
Improper initialization of CPU cache memory could allow a privileged attacker with hypervisor access to overwrite SEV-S…
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Low 3.2
Incomplete cleanup after loading a CPU microcode patch may allow a privileged attacker to degrade the entropy of the RD…
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Low 3.8
A transient execution vulnerability in some AMD processors may allow a user process to infer the control registers spec…
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Low 3.8
A transient execution vulnerability in some AMD processors may allow a user process to infer TSC_AUX even when such a r…